Delay circuit applied to semiconductor memory device having auto power-down function

ABSTRACT

A delay circuit comprises a charge/discharge circuit and a logic circuit. The charge/discharge circuit is used to moderate a slope of change of an input signal. The logic circuit receives a charge/discharge signal output from the charge/discharge circuit, and is used to change an output signal of the logic circuit when the charge/discharge signal exceeds a threshold value of the logic circuit. A time constant in the charge/discharge circuit is varied in accordance with the change in the output signal of the logic circuit. This serves to alleviate the malfunctioning and timing constraint problems that occur after the threshold value of the next-stage circuit (logic circuit) is exceeded.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a delay circuit and asemiconductor memory device, and more particularly to a delay circuitthat is applied to a semiconductor device having an auto power-downfunction.

[0003] 2. Description of the Related Art

[0004] With increasing functional complexity in various kinds ofcircuits in recent years, it has come to be widely practiced to supplysignals by delaying signal timing. This trend has brought a need for adelay circuit which can change its delay time, requires fewercomponents, and consumes less current, and which can output a delayedsignal without being affected by noise or by fluctuations in supplypower.

[0005] Namely, in the prior art, a delay circuit (CR delay circuit)comprises, for example, a resistor, a capacitor, and an inverter. Notethat, the voltage change of the input signal is slowed by a timeconstant (T=CR) of the resistor and capacitor, thereby delaying thetiming at which the input voltage to the inverter at the next stageexceeds the threshold voltage of the inverter. In this way, an outputsignal, which is delayed with respect to the input signal of the delaycircuit, can be obtained.

[0006] However, in the prior art delay circuit, the input voltage of theinverter is determined only by the time constant of the resistor andcapacitor, and thus the change of the voltage is still slow after thethreshold voltage is exceeded. Therefore, if the input voltagefluctuates, and if the input voltage of the inverter drops again belowthe threshold voltage, an unwanted pulse may be included in the outputsignal.

[0007] The prior art delay circuit and problems associated with theprior art delay circuit will be described in detail later with referenceto drawings.

SUMMARY OF THE INVENTION

[0008] An object of the present invention is to provide a delay circuitcapable of alleviating the malfunctioning and timing constraint problemsthat occur after the threshold value of the next-stage circuit isexceeded. It is also an object of the present invention to provide asemiconductor memory device incorporating such a delay circuit.

[0009] According to the present invention, there is provided a delaycircuit comprising a charge/discharge circuit for moderating a slope ofchange of an input signal; and a logic circuit, receiving acharge/discharge signal output from the charge/discharge circuit, forchanging an output signal of the logic circuit when the charge/dischargesignal exceeds a threshold value of the logic circuit, wherein a timeconstant in the charge/discharge circuit is varied in accordance withthe change in the output signal of the logic circuit.

[0010] Further, according to the present invention, there is alsoprovided a semiconductor memory device having a cell matrix having aplurality of memory cells; a data latch for latching readout data outputfrom the cell matrix; an address transfer detection circuit fordetecting an address signal change; a delay circuit, outputting a latchcontrol signal to the data latch in accordance with an output signal ofthe address transfer detection circuit, for controlling the data latchto output the readout data in synchronism with the latch control signal,wherein the delay circuit comprises a charge/discharge circuit formoderating a slope of change of an input signal; and a logic circuit,receiving a charge/discharge signal output from the charge/dischargecircuit, for changing an output signal of the logic circuit when thecharge/discharge signal exceeds a threshold value of the logic circuit,wherein a time constant in the charge/discharge circuit is varied inaccordance with the change in the output signal of the logic circuit.

[0011] The charge/discharge circuit may comprise a switch element whoseone end is connected to an input of the logic circuit, and a capacitorelement whose one end is connected to the other end of the switchelement, wherein a switching operation of the switch element may becontrolled by the output signal of the logic circuit to vary the timeconstant of the charge/discharge circuit due to the capacitor element.The switch element may be controlled in such a manner as to be switchedOFF by the output signal of the logic circuit when the output signal ofthe logic circuit changes in response to the charge/discharge signalexceeding the threshold value of the logic circuit.

[0012] There may be provided a plurality of the capacitor elements whoseconnection to the input of the logic circuit is controlled by the switchelement, and the plurality of capacitor elements may be arranged inparallel with each other. At least one of the plurality of capacitorelements may be connected, at one end, to the other end of the switchelement and at the other end to a prescribed power supply line. At leastone of the plurality of capacitor elements may be connected at one endto the other end of the switch element and at-the other end to an outputof a driver circuit supplied with a prescribed control signal.

[0013] The charge/discharge circuit may be inserted in an input of thelogic circuit, and may comprise a resistor element for supplying theinput signal via the resistor element, and a switch element disposed inparallel with the resistor element, wherein a switching operation of theswitch element may be controlled by the output signal of the logiccircuit to vary the time constant of the charge/discharge circuit due tothe resistor element. The switch element may be controlled in such amanner as to be switched ON by the output signal of the logic circuitwhen the output signal of the logic circuit changes in response to thecharge/discharge signal exceeding the threshold value of the logiccircuit. There may be provided a plurality of the switch elements and aplurality of the resistor elements whose short-circuiting with the inputof the logic circuit is controlled by the switch element, and theplurality of switch elements and the plurality of resistor elements maybe respectively arranged in series with each other. The plurality ofswitch elements for controlling the short-circuiting of the plurality ofresistor elements may be each controlled for switching, by the outputsignal of the logic circuit.

[0014] The charge/discharge circuit may include a current source, and acurrent flowing through the current source may be controlled by theoutput signal of the logic circuit. The current flowing through thecurrent source may be controlled so that the current increases when theoutput signal of the logic circuit changes in response to thecharge/discharge signal exceeding the threshold value of the logiccircuit. The logic circuit may comprise a comparator, a first inputterminal of which is supplied with the charge/discharge signal from thecharge/discharge circuit, and a second input terminal of which issupplied with a reference voltage, wherein a control may be carried outto vary the reference voltage in accordance with the output signal ofthe logic circuit.

[0015] The logic circuit may comprise a CMOS inverter. The capacitorelement may be constituted as a CMOS capacitor. The semiconductor memorydevice may be a flash EEPROM.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present invention will be more clearly understood from thedescription of the preferred embodiments as set forth below withreference to the accompanying drawings, wherein:

[0017]FIG. 1 is a circuit diagram showing an example of a delay circuitaccording to the prior art;

[0018]FIG. 2 is a waveform diagram for explaining a problem associatedwith the delay circuit shown in FIG. 1;

[0019]FIG. 3 is a circuit diagram showing another example of a delaycircuit according to the prior art;

[0020]FIG. 4 is a waveform diagram for explaining a problem associatedwith the delay circuit shown in FIG. 3;

[0021]FIG. 5 is a block diagram showing a configuration of a flashEEPROM as an example of a semiconductor memory device incorporating adelay circuit according to the present invention;

[0022]FIG. 6 is a waveform diagram for explaining a read operation ofthe flash EEPROM shown in FIG. 5;

[0023]FIG. 7 is a waveform diagram for explaining an auto power-downoperation of the flash EEPROM shown in FIG. 5;

[0024]FIG. 8 is a circuit diagram showing a basic functionalconfiguration of a delay circuit according to the present invention;

[0025]FIG. 9 is a waveform diagram for explaining an operation of thedelay circuit shown in FIG. 8;

[0026]FIG. 10 is a circuit diagram showing a first embodiment of a delaycircuit according to the present invention;

[0027]FIG. 11 is a waveform diagram for explaining an operation of thedelay circuit shown in FIG. 10;

[0028]FIG. 12 is a circuit diagram showing a modified example of thedelay circuit shown in FIG. 10;

[0029]FIG. 13 is a circuit diagram showing a second embodiment of adelay circuit according to the present invention;

[0030]FIG. 14 is a waveform diagram for explaining an operation of thedelay circuit shown in FIG. 13;

[0031]FIG. 15 is a circuit diagram showing a modified example of thedelay circuit shown in FIG. 13;

[0032]FIG. 16 is a circuit diagram showing a third embodiment of a delaycircuit according to the present invention;

[0033]FIG. 17 is a waveform diagram for explaining an operation of thedelay circuit shown in FIG. 16;

[0034]FIG. 18 is a circuit diagram showing a fourth embodiment of adelay circuit according to the present invention;

[0035]FIG. 19 is a waveform diagram for explaining an operation of thedelay circuit shown in FIG. 18;

[0036]FIG. 20 is a circuit diagram showing a fifth embodiment of a delaycircuit according to the present invention; and

[0037]FIG. 21 is a waveform diagram for explaining an operation of thedelay circuit shown in FIG. 20.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] Before describing the preferred embodiments of the delay circuitaccording to the present invention, a prior art delay circuit andproblems associated with the prior art delay circuit will be describedwith reference to FIGS. 1 to 4.

[0039]FIG. 1 is a circuit diagram showing one example of the prior artdelay circuit.

[0040] As shown in FIG. 1, the prior art delay circuit (CR delaycircuit) comprises, for example, a resistor 1, a capacitor 2, and aninverter 3. More specifically, the resistor 1 is inserted between aninput (IN) of the delay circuit and a node N1 (input of the inverter 3),and the capacitor 2 is provided between the node N1 and a ground line(GND; Vss). The configuration is such that, with the time constant(T=CR) of the resistor 1 and capacitor 2, the voltage change of theinput signal IN is slowed thereby delaying the timing at which the inputvoltage (voltage at the node N1) to the inverter 3 at the next stageexceeds the threshold voltage Vth of the inverter 3. In this way, anoutput signal OUT (equal to the input signal but with inverted level),delayed with respect to the input signal IN of the delay circuit, can beobtained. Here, the resistor 1 and the capacitor 2 together constitute acharging circuit (charge/discharge circuit). The inverter 3 may bereplaced by another logic circuit having a prescribed threshold value.

[0041]FIG. 2 is a waveform diagram for explaining the problem of thedelay circuit shown in FIG. 1.

[0042] As shown in FIG. 2, when the input signal IN changes from a lowlevel “L” (low-level supply voltage Vss) to a high level “H” (high-levelsupply voltage Vcc), the input voltage (N1) to the inverter 3 slowlyrises in accordance with the time constant of the resistor 1 andcapacitor 2, and when the threshold voltage Vth of the inverter 3 isexceeded, the output signal OUT with inverted level is output.

[0043] However, in the prior art delay circuit shown in FIG. 1, sincethe input voltage (N1) to the inverter 3 is determined only by the timeconstant of the resistor 1 and capacitor 2, the change of the voltage(N1) is still slow after the threshold voltage is exceeded. Therefore,if the input voltage IN fluctuates (see reference sign F in FIG. 2), forexample, because of the effects of noise or fluctuating supply voltage,and if the input voltage (N1) to the inverter 3 drops again below thethreshold voltage Vth, an unwanted portion (unwanted pulse E) will beincluded in the output signal OUT; this can lead to the malfunctioningof a circuit operating by receiving the output signal (delayed output)OUT.

[0044]FIG. 3 is a circuit diagram showing another example of the priorart delay circuit.

[0045] As shown in FIG. 3, the delay circuit comprises, for example, aresistor 1, N-channel MOS transistors 20 and 21, a CMOS inverter 3, anda driver (CMOS inverter) 5. Here, the transistors 20 and 21 are eachused as a MOS capacitor with source and drain connected together. Oneend of each of the MOS capacitors (transistors) 20 and 21 is connectedto the input (node N1) of the inverter 3, while the other end (sourceand drain) of the MOS capacitor 20 is connected to a high-level voltagesupply line (Vcc), and the other end (source and drain) of the MOScapacitor 21 is connected to the output of the inverter (driver) 5 whoseinput is supplied with a control signal Si. Here, the resistor 1 and theMOS capacitors 20 and 21 together constitute a charging circuit(charge/discharge circuit).

[0046] The delay circuit shown in FIG. 3 is configured to vary therising slope of the input voltage (N1) to the inverter 3 by controllingthe contribution (connection) of the MOS capacitor 21 by the controlsignal S1.

[0047]FIG. 4 is a waveform diagram for explaining the problem of thedelay circuit shown in FIG. 3.

[0048] As shown in FIG. 4, when the control sinal S1 is at a low level“L” (low-level supply voltage Vss), the output (the other end of the MOScapacitor 21) of the inverter 5 is at a high level “H” (high-levelsupply voltage Vcc). Here, since the high-level supply voltage Vcc isalso supplied to the other end of the MOS capacitor 20, when the inputsignal IN changes from the low level “L” to the high level “H” the levelof the node N1 (input voltage to the inverter 3) rises slowly, as shownby reference sign L1 in FIG. 4, because the two MOS capacitors 20 and 21are both contributing.

[0049] After the input voltage (N1) to the inverter 3 exceeds thethreshold voltage Vth of the inverter 3, when the control signal S1changes from the low level “L” to the high level “H” the output (theother end of the MOS capacitor 21) of the inverter 5 is driven to thelow level “L”, so that the charge on the node N1 (the charge stored inthe MOS capacitors 20 and 21) is released through the MOS capacitor 21.As a result, the input voltage (N1) to the inverter 3 drops again belowthe threshold voltage Vth of the inverter 3, as shown by reference signF in FIG. 4, and an unwanted portion (unwanted pulse) P is included inthe output voltage OUT.

[0050] That is, in the configuration where the MOS capacitor 21 isisolated by using the control signal S1, the input voltage (N1) to theinverter 3 may drop again below the threshold voltage Vth because of thedischarging action of the isolated MOS capacitor 21, depending on thetiming of the control signal S1. This timing problem imposes aconstraint on circuit operation.

[0051] The problem described with reference to FIGS. 3 and 4 occurs, forexample, when the delay circuit is applied to a flash EEPROM (flashmemory).

[0052] Next, a flash EEPROM, as an example of a semiconductor memorydevice, and a read operation and auto power-down operation of the flashEEPROM will be described with reference to FIGS. 5 to 7.

[0053]FIG. 5 is a block diagram showing the configuration of a flashEEPROM, as an example of a semiconductor memory device, incorporatingthe delay circuit. In FIG. 5, reference numeral 100 is the delaycircuit, 101 is a command register state machine, 102 is a chipenable/output enable logic, 103 is an address register, 104 is anaddress transfer detection circuit, 105 is a timer, 106 is an erasingvoltage generating circuit, and 107 is a program voltage (writingvoltage) generating circuit. Further, reference numeral 108 is a columndecoder, 109 is a row decoder, 110 is an input/output buffer, 111 is adata latch, 112 is a Y selection circuit, and 113 is a cell matrix.

[0054] As shown in FIG. 5, the command register state machine 101 issupplied with a reset signal /RESET, a write enable signal /WE, and achip enable signal /CE, as well as an output from the timer 105 and anoutput signal from the chip enable/output enable logic 102, and controlsthe erasing voltage generating circuit 106, the program voltagegenerating circuit 107, etc. by supplying control signals in accordancewith the signals /RESET, /WE, and /CE. The chip enable/output enablelogic 102 receives the chip enable signal /CE and output enable signal/OE, and controls the input/output buffer 110, etc.

[0055] The input/output buffer 110 is used to transfer data to and froman I/O circuit; that is, data (readout output data DD2) from the datalatch Ill is output to the I/O circuit, and data (write data, commanddata, etc.) from the I/O circuit is transferred to the data latch 111and command register state machine 110.

[0056] The address register 103 receives an address signal ADD andsupplies a column address and row address to the column decoder 108 androw decoder 109, respectively, and a cell (memory cell) in the cellmatrix (memory cell array) 113, specified by the address signal ADD, isselected. More specifically, a word line is selected by the row decoder109, and at the same time, a bit line is selected by the Y selectioncircuit 112 controlled by the column decoder 108, to write or read datain the cell specified by the address signal ADD. Here, the high-levelvoltage (program voltage) used when writing is supplied from the programvoltage generating circuit 107 to the column decoder 108, and appliedvia the Y selection circuit 112 to the cell specified by the addresssignal ADD. On the other hand, the output voltage (erasing voltage) fromthe erasing voltage generating circuit 106 is supplied to the rowdecoder 109, and is used to erase the entire data in the eell matrix113.

[0057] The address signal ADD is also supplied to the address transferdetection circuit 104 which then detects the transfer of the addresssignal. An output (an address transfer detection signal SS1) of theaddress transfer detection circuit 104 is supplied to the delay circuit100, and using an output (SS2) of the delay circuit 100, the operation(latch operation) of the data latch 111 is controlled. Morespecifically, the data latch 111 latches the memory readout data DD1supplied via the Y selection circuit 112, in synchronism with the outputsignal (latch control signal) SS2 of the delay circuit 100, and outputsthe output data DD2 via the input/output buffer 110.

[0058] In this way, the above-described delay circuit (the delay circuitcontemplated by the present invention) is applied, for example, as thedelay circuit 100 in the flash EEPROM. This flash EEPROM has an autopower-down function by which internal circuitry is powered down when noaddress change occurs, for example, within a specified period of time.

[0059]FIG. 6 is a waveform diagram for explaining the read operation ofthe flash EEPROM shown in FIG. 5. In the read operation of the flashEEPROM which has an auto power-down operation, the output from thememory cell (cell matrix 113) must be latched by the data latch 111because the internal circuits are powered down if, after changing theaddress by selecting a device (memory cell), the address does not changeagain within a specified period of time, for example. More specifically,since it takes, for example, more than several tens of nanosecondsbefore data read out of a memory cell stabilizes, the latch controlsignal (SS2) is output after more than several tens of nanoseconds haselapsed from the detection of an address change, to latch the readoutdata DD1 into the data latch 111.

[0060] As shown in FIG. 6, in a usual read operation, when the addresssignal ADD changes, the address transfer detection circuit 104 detectsthe change (transfer) of the address signal ADD, and outputs the addresstransfer detection signal SS1 to the delay circuit 100. The delaycircuit 100 is also supplied with a power-down signal (control signal)S1. From the delay circuit 100, the latch control signal SS2 having apulse P0 is supplied to the data latch 111 when the node N1 (inputsignal to the inverter 3 in FIG. 3) exceeds the threshold value Vth.Then, the data latch 111 latches the readout data DD1 in synchronism,for example, with the pulse P0 of the latch control signal SS2.

[0061] The latch control signal SS2 here is obtained, for example, as anoutput signal OUT from an RC delay circuit, such as shown in FIG. 3, forthe address transfer detection signal SS1 as the input signal IN. Thisdelay circuit is designed to be capable of changing theresistor/capacitor time constant (delay time), by considering caseswhere there is a performance margin, due to variations in processconditions, to speed up the device access time, or where stable DC-likemeasurements are needed when evaluating the device. The control signal(S1) for switching the delay time is programmed in the memory (flashEEPROM) to control the contribution (connection) of the capacitor (MOScapacitor).

[0062]FIG. 7 is a waveform diagram for explaining the auto power-downoperation of the flash EEPROM shown in FIG. 5.

[0063] Normally, the above delay-time switching control signal (S1) doesnot change, but when the auto power-down function is activated, forexample, the above delay-time switching control signal S1 cannot be readout correctly because the circuit for reading the memory (memory cell113) is also powered down. As a result, the same problem as describedwith reference to FIGS. 3 and 4 may occur, as shown in FIG. 7 (seereference sign N1). That is, in addition to the normal pulse P0, a pulse(unwanted pulse) P1 occurs in the latch control signal SS2 (outputsignal OUT of the delay circuit 100) that is supplied from the delaycircuit 100 to the data latch 111. As a result, the data latch 111operating based on the pulses (P0, P1) of the latch control signal SS2malfunctions, or it becomes necessary to impose a constraint on theoperating timing in order to prevent the malfunctioning.

[0064] In this way, as explained with reference to FIG. 2, for example,the prior art delay circuit is so susceptible to the effects of noise,variations in supply voltage, etc. that even after the input voltageexceeds the threshold value of the next-stage circuit (inverter), theinput voltage tends to drop again below the threshold value of thenext-stage circuit. This tendency becomes more pronounced as thecapacitance value is made larger for increased delay time, thus tendingto cause circuit malfunctioning more easily.

[0065] Furthermore, as explained with reference to FIG. 3 or 7, in theprior art delay circuit and the semiconductor memory device (flashEEPROM) incorporating the prior art delay circuit, when the capacitor isconstructed from an active device such as an N-channel MOS transistorand is so configured as to be isolated using a control signal (S1), forexample, there occurs the possibility of the input voltage droppingbelow the threshold value of the next-stage circuit because ofdischarging unless the control signal is input after the active deviceis turned OFF. To prevent this, a constraint has to be imposed oncircuit operation timing.

[0066] The preferred embodiments of the delay circuit according to thepresent invention will now be described below with reference to theaccompanying drawings.

[0067]FIG. 8 is a circuit diagram showing the basic functionalconfiguration of the delay circuit according to the present invention.In FIG. 8, reference numeral 1 is a resistor (resistor element), 2 is acapacitor (capacitor element), 3 is an inverter, and 4 is a switch means(switch element).

[0068] As is apparent from the comparison with the prior art delaycircuit shown in FIG. 1, the delay circuit of the present inventionshown in FIG. 8 differs from the delay circuit of FIG. 1 by theinclusion of the switch element 4 which is connected between the node N1and one end of the capacitor 2 and which is controlled by the outputsignal of the inverter 3.

[0069] More specifically, the resistor 1 is provided between the input(IN) of the delay circuit and the node N1 (input of the inverter 3),while the switch element 4 and the capacitor 2 are connected in seriesbetween the node N1 and the ground line (GND, Vss). In the initialstate, the switch element 4 is ON, so that as in the prior art delaycircuit shown in FIG. 1, with the time constant (T=CR) of the resistor 1and capacitor 2 the voltage change of the input signal IN is slowedthereby delaying the timing at which the input voltage (voltage at thenode N1: charge/discharge voltage) to the inverter 3 at the next stageexceeds the threshold voltage Vth of the inverter 3. An output signalOUT (equal to the input signal but with inverted level), delayed withrespect to the input signal IN of the delay circuit, is thus produced.Here, the resistor 1 and the capacitor 2 together constitute a chargingcircuit (charge/discharge circuit). The inverter 3 may be replaced byanother logic circuit or the like having a threshold value.

[0070] In the delay circuit of the present invention, the switch element4, in response to a change in the output signal OUT, is switched fromthe ON to the OFF state, thereby isolating the capacitor 2 from the nodeN1 and allowing the change of the input signal IN to be applied directlyto the node N1 (the input of the inverter 3).

[0071]FIG. 9 is a waveform diagram for explaining the operation of thedelay circuit shown in FIG. 8.

[0072] As shown in FIG. 9, when the input signal (step signal) INchanges from a low level “L” (low-level supply voltage Vss) to a highlevel “H” (high-level supply voltage Vcc), the input voltage (N1) to theinverter 3 slowly rises in accordance with the time constant of theresistor 1 and capacitor 2, and when the threshold voltage Vth of theinverter 3 is exceeded, the output signal OUT with inverted level (lowlevel “L”) is output. In response to the output signal OUT thus changingfrom the high level “H” to the low level “L”, the switch element 4changes from the ON state to the OFF state, and the capacitor 2 isisolated from the node N1.

[0073] As a result, the input signal IN is supplied to the input of theinverter 3 without being slowed by the capacitor 2. In this way, if theinput signal IN fluctuates (as shown by reference sign F in FIG. 9)because of the effects of noise and variations in supply voltage, forexample, since the input voltage (N1) to the inverter 3 has alreadyrisen to the high level “H” the input signal N1 does not drop below thethreshold voltage Vth of the inverter 3, eliminating the possibility ofan unwanted portion being included in the output signal OUT. Therefore,after the output signal has changed (delayed output is output), even ifthe input signal IN fluctuates because of the effects of noise,variations in supply voltage, etc., no unwanted changes occur in theoutput signal OUT because the margin against noise is large. This servesto prevent the malfunctioning of the circuit operating by receiving theoutput signal OUT.

[0074]FIG. 10 is a circuit diagram showing a first embodiment of thedelay circuit according to the present invention.

[0075] As shown in FIG. 10, the delay circuit comprises, for example, aresistor 1, N-channel MOS transistors 4, 20, and 21, an inverter (CMOSinverter) 3, and a driver (CMOS inverter) 5. Here, the transistors 20and 21 are each used as a MOS capacitor with source and drain connectedtogether. One end of each of the MOS capacitors (transistors) 20 and 21is connected to the input (node N1) of the inverter 3, while the otherend (source and drain) of the MOS capacitor 20 is connected to ahigh-level voltage supply line (Vcc), and the other end (source anddrain) of the MOS capacitor 21 is connected to the output of theinverter (driver) 5 whose input is supplied with a control signal S1.Here, the resistor 1 and the MOS capacitors 20 and 21 togetherconstitute a charging circuit (charge/discharge means).

[0076] The delay circuit shown in FIG. 10 differs from the prior artdelay circuit shown in FIG. 3 by the inclusion of the transistor (switchelement) 4 which is connected between the node N1 and one end of the MOScapacitor 21 and whose gate is coupled to the output (output signal OUT)of the inverter 3. More specifically, the configuration is such thatusing the control signal S1, the contribution (connection) of the MOScapacitor 21 is controlled to vary the rising slope of the input voltage(N1: charge/discharge signal) to the inverter 3, and when the thresholdvoltage Vth is exceeded thereby causing the output of the inverter 3 toinvert, the transistor 4 is switched OFF to isolate the MOS capacitor 21from the node N1.

[0077]FIG. 11 is a waveform diagram for explaining the operation of thedelay circuit shown in FIG. 10.

[0078] As shown in FIG. 11, when the control signal S1 is at a low level“L” (Vss), the output (the other end of the MOS capacitor 21) of theinverter 5 is at a high level “H” (Vcc). The high-level supply voltageVcc is also applied to the other end of the MOS capacitor 20. Here,since the signal (output signal OUT) supplied to the gate of theN-channel MOS transistor 4 is at the high level “H”, the transistor 4 isON. Therefore, when the input signal IN changes from the low level “L”to the high level “H”, the voltage at the node N1 (input voltage to theinverter 3) slowly rises, as shown by reference sign L1 in FIG. 11,because of accumulation of charge on the two MOS capacitors 20 and 21(both capacitors are contributing).

[0079] Then, when the input voltage (N1) to the inverter 3 exceeds thethreshold voltage Vth of the inverter 3, the output signal OUT isinverted from the high level “H” to the low level “L”, and by thislow-level output signal OUT, the transistor 4 is switched OFF. Thiscauses the two MOS capacitors 20 and 21 to be isolated from the node N1,allowing the level of the node N1 to rise rapidly to the high level “H”.

[0080] Thereafter, when the control signal S1 changes from the low level“L” to the high level “H”, the output of the inverter 5 (the other endof the MOS capacitor 21) goes to the low level “L” (Vss), but since thetransistor 4 is already switched OFF, the charge on the node N1 will notbe discharged. The node N1 (input voltage to the inverter 3) is thusmaintained at the high level “H”. This prevents the input voltage (N1)to the inverter 3 from dropping again below the threshold voltage Vth ofthe inverter 3, and eliminates the possibility of an unwanted portion(unwanted pulse P) being included in the output voltage OUT. Thisprovides greater freedom in circuit design since no constraints have tobe imposed by circuit operation timing.

[0081] As described above, according to the first embodiment of thepresent invention, when the input voltage to the inverter 3 exceeds thethreshold voltage Vth, the transistor 4 is switched OFF to isolate theMOS capacitors 20 and 21 from the node N1. As a result, the timeconstant of the node N1 is reduced, and the node N1 rises rapidly to thehigh level “H”, departing quickly from the threshold value Vth. Thisserves to reduce the chance of being subjected to the effects of noise,etc. and also keep the node N1 from being affected by the discharging ofthe MOS capacitor 21 by the control signal S1.

[0082]FIG. 12 is a circuit diagram showing a modified example of thedelay circuit of FIG. 10. As is apparent from the comparison between thedelay circuits shown in FIGS. 10 and 12, the modified example ischaracterized by the provision of a plurality of MOS capacitors 21(three in the illustrated example) whose connection (contribution) iscontrolled by the control signal S1. More specifically, in the modifiedexample of FIG. 12, N-channel MOS transistors (MOS capacitors) 20 and211 to 213 are provided, each with its drain and source connectedtogether, and one end of each of these MOS capacitors is connected tothe node N1 (input of the inverter) via the transistor 4. The other endof the MOS capacitor 20 is supplied with the high-level supply voltageVcc, while the other ends of the MOS capacitors 211 to 213 arerespectively supplied with control signals S11 to S13 via drivers (MOSinverters) 51 to 53, respectively. The resistor 1 and the MOScapacitors, 20 and 211 to 213, together constitute the charging circuit(charge/discharge circuit).

[0083] Here, the capacitance values of the MOS capacitors 211 to 213 maybe set identical, or may be set in proportions of 1:2:4 as powers of 2,or may be set in various ways as needed. The connections (contributions)of these MOS capacitors 211 to 213 are controlled by the control signalsS11 to S13 to obtain the necessary delay time. The operation of thetransistor 4, etc. is the same as the first embodiment shown in FIGS. 10and 11.

[0084]FIG. 13 is a circuit diagram showing a second embodiment of thedelay circuit according to the present invention.

[0085] As shown in FIG. 13, the delay circuit comprises, for example, aresistor 1, a capacitor 2, an inverter (CMOS inverter) 3, and aP-channel MOS transistor 6.

[0086] In the delay circuit shown in FIG. 13, the transistor 6 isconnected in parallel with the resistor 1, and the output signal OUT isapplied to the gate of the transistor 6. More specifically, in responseto a level change of the output signal OUT, the resistor 1 isshort-circuited by the transistor 6 so that the input signal IN issupplied directly (via the transistor 6) to the node N1. The resistor 1and the capacitor 2 together constitute a charging circuit(charge/discharge circuit).

[0087]FIG. 14 is a waveform diagram for explaining the operation of thedelay circuit shown in FIG. 13.

[0088] As shown in FIG. 14, when the input signal IN changes from a lowlevel “L” to a high level “H”, the input voltage (N1: charge/dischargesignal) to the inverter 3 slowly rises in accordance with the timeconstant (T=RC) of the resistor 1 and capacitor 2, and when thethreshold voltage Vth of the inverter 3 is exceeded, the output signalOUT with inverted level (low level “L”) is output. In response to theoutput signal OUT thus changing from the high level “H” to the low level“L”, the P-channel MOS transistor 6 changes from the OFF state to the ONstate, and thus the resistor 1 is short-circuited by the transistor 6.In this condition, the input signal IN is supplied via the transistor 6to the node N1, thereby reducing the value of the time constant (T=RC)due to the resistor 1 and capacitor 2, and thus allowing the node N1 torise rapidly to the high level “H” (Vcc).

[0089] As a result, after the output signal has changed, even if theinput signal IN fluctuates because of the effects of noise, variationsin supply voltage, etc., no unwanted changes occur in the output signalOUT because the margin against noise is large. This serves to preventthe malfunctioning of the circuit operating by receiving the outputsignal OUT.

[0090]FIG. 15 is a circuit diagram showing a modified example of thedelay circuit of FIG. 13. As is apparent from the comparison between thedelay circuits shown in FIGS. 13 and 15, the modified example ischaracterized by the provision of a plurality of resistors 1 and aplurality of P-channel MOS transistors 6 (two such sets are provided inthe illustrated example). More specifically, in the modified example ofFIG. 15, two sets, each set consisting of the same elements as theresistor 1, capacitor 2, and transistor 6 shown in FIG. 13, areconnected in series (that is, the resistor 11, capacitor 21, andtransistor 61 between the input IN and node Nil, and the resistor 12,capacitor 22, and transistor 62 between the node N11 and node N12), andthe output signal OUT is applied to the gates of the P-channel MOStransistors 61 and 62. With this configuration, the time constant whenthe transistors 61 and 62 are both OFF is increased to increase thecircuit delay time. Here, the resistors 11 and 12 and capacitors 21 and22 constitute the charging circuit (charge/discharge circuit). Theoperation of the transistors 61 and 62, etc. is the same as the secondembodiment shown in FIGS. 13 and 14.

[0091]FIG. 16 is a circuit diagram showing a third embodiment of thedelay circuit according to the present invention, and FIG. 17 is awaveform diagram for explaining the operation of the delay circuit shownin FIG. 16.

[0092] As shown in FIG. 16, the delay circuit of the third embodimentcomprises a capacitor (capacitor elements) 2, inverters 3 and 79, aplurality of P-channel MOS transistors 71 to 75, an N-channel MOStransistor 76, and resistors (resistor elements) 77 and 78.

[0093] Here, the transistors 72 and 75 are connected in a current mirrorarrangement (current mirror connection) so that the current ir flowingthrough the transistor 72 on the reference side is equal to the currenti0 flowing through the transistor 75 on the current drawing side. Theresistor 78 is a resistor which is provided to set the reference currentand through which a current i1 flows. Into the resistor 77 flows acurrent i2 via the transistor 71 whose gate is supplied with a referencecurrent adjusting control signal S3. The output signal OUT of theinverter 3 is used as the control signal S3. Accordingly, the transistor71 is OFF when the control signal S3 (output signal OUT) is at the highlevel “H”, and ON when it is at the low level “L”. Here, the currentsource 75 and the capacitor 2 together constitute a charging circuit(charge/discharge circuit).

[0094] The transistors 73 and 74 function as switches to control theisolation of the current source by the input signal IN, while thetransistor 76 functions as a pull-down transistor.

[0095] As shown in FIG. 17, when the input signal IN is at the low level“L” (Vss), the N-channel MOS transistor 76 is ON, so that the voltage atthe node N1 is pulled down to the low level “L”. On the other hand, theP-channel MOS transistor 73 is ON, and the transistor 74 is OFF. As aresult, the high level “H” (Vcc) is applied to the gate of the P-channelMOS transistor 75, so that the transistor 75 is OFF. The transistor 74acts as a switch to prevent the current from the high-level power supplyVcc side from being supplied to the resistor 78 when the gate and drainof the transistor 72 are connected together.

[0096] Next, when the input signal IN goes to the high level “H”, thetransistor 76 is switched OFF, while the transistor 73 is switched OFFand the transistor 74 is switched ON. As a result, the currenti1=(Vcc−Vth0)/R1 flows to the resistor 78. If the transistors 72 and 75are identical in size, the current i1 flows through the transistor 75.Then, the voltage (charge/discharge signal) at the node N1 rises with(i1/C)t, where t is the time.

[0097] When the voltage at the node N1 exceeds the threshold value Vthof the inverter 3, the output OUT changes from the high level “H” to thelow level “L”, and the transistor 71 is switched ON. As a result, thecurrent i is i1=i1+i2=(Vcc−Vth0)/(R1//R2) Since the transistors 72 and75 are connected in a current mirror arrangement, it follows that ir=i0;therefore, if the current i2 is set sufficiently large, the node N1rises rapidly.

[0098] In this way, the third embodiment achieves the same effect asobtained in the foregoing second embodiment. Further, if the inputcapacitance of the inverter 3 is large, and if the current i1 is setsufficiently small and the current i2 sufficiently large, then thecapacitor 2 need not be provided. It will also be recognized thatvarious circuit configurations are possible for the current source.

[0099]FIG. 18 is a circuit diagram showing a fourth embodiment of thedelay circuit according to the present invention.

[0100] The delay circuit of the fourth embodiment shown in FIG. 18 is acombination of the previously described basic functional configuration(with reference to FIG. 8) and the configuration of the secondembodiment (with reference to FIG. 13). More specifically, the N-channelMOS transistor (switch element) 4, whose gate is supplied with theoutput signal OUT, is provided between the input (node N1) of theinverter 3 and the capacitor (MOS capacitor) 2, while the P-channel MOStransistor (switch element) 6, whose gate is supplied with the outputsignal OUT, is connected in parallel with the resistor 1. Here, theresistor 1 and the capacitor 2 together constitute a charging circuit(charge/discharge circuit).

[0101]FIG. 19 is a waveform diagram for explaining the operation of thedelay circuit shown in FIG. 18.

[0102] As shown in FIG. 19, when the input signal IN is at a low level“L”, and the output signal OUT is at a high level “H”, the N-channel MOStransistor 4 is ON and the P-channel MOS transistor 6 is OFF.Accordingly, the input signal N1 slowly rises in accordance with thetime constant (T=RC) of the resistor 1 and capacitor 2, and when thethreshold voltage Vth of the inverter 3 is exceeded, the output signalOUT with inverted level (low level “L”) is output. In response to theoutput signal OUT thus changing from the high level “H” to the low level“L”, the N-channel MOS transistor 4 changes from the ON state to the OFFstate, and the P-channel MOS transistor 6 changes from the OFF state tothe ON state. As a result, the MOS capacitor 2 is isolated from the nodeN1, and the resistor 1 is short-circuited by the transistor 6, allowingthe node N1 to rise rapidly to the high level “H” (Vcc).

[0103] Therefore, after the output signal has changed, even if the inputsignal IN fluctuates because of the effects of noise, variations insupply voltage, etc., no unwanted changes occur in the output signal OUTbecause the margin against noise is large. This serves to prevent themalfunctioning of the circuit operating by receiving the output signalOUT.

[0104]FIG. 20 is a circuit diagram showing a fifth embodiment of thedelay circuit according to the present invention.

[0105] As shown in FIG. 20, the delay circuit of the fifth embodimentuses a comparator 9; the input signal IN is applied via the resistor 1to a positive logic input (node N1) of the comparator 9, and the node N1is connected to the capacitor 2 whose other end is grounded (connectedto the low-level voltage supply line (GND; Vss)). The output signal OUTis supplied to the gate of an N-channel MOS transistor (switch element)84 to control the connection between the high-level voltage supply line(Vcc) and one end of a resistor 83. The other end of the resistor 83 isconnected to a negative logic input (node N2) of the comparator 9, andalso to the high-level voltage supply line (Vcc) via a resistor R81 andthe low-level voltage supply line (Vss) via a resistor R82. That is, thenegative logic input of the comparator 9 is supplied with a voltage V1divided through the resistors R81 and 83 and resistor R82 (when thetransistor 84 is ON), or with a voltage V2 divided through the resistorsR81 and R82 (when the transistor 84 is OFF). The relation V1>V2 holdsbetween the voltage V1 and voltage V2.

[0106]FIG. 21 is a waveform diagram for explaining the operation of thedelay circuit shown in FIG. 20.

[0107] As shown in FIG. 21, when the input signal IN is at a low level“L”, and the output signal OUT is at a high level “H”, the N-channel MOStransistor 84 is ON, so that the voltage at the node N2 (the voltageapplied to the negative logic input of the comparator 9) is equal to thevoltage V1 (>V2) divided through the resistors R81 and 83 and resistorR82.

[0108] The input signal IN slowly rises in accordance with the timeconstant (T=RC) of the resistor 1 and MOS capacitor 2, and when thevoltage at the node N1 (the voltage applied to the positive logic inputof the comparator 9) exceeds the voltage at the node N2 (the voltageapplied to the negative logic input of the comparator 9), the outputsignal OUT changes from the high level “H” to the low level “L”. Inresponse to the output signal OUT changing to the low level “L”, theN-channel MOS transistor 84 is switched OFF, and the resistor 83 is thusisolated from the high-level voltage supply line (Vcc). As a result, thevoltage at the node N2 (the voltage applied to the negative logic inputof the comparator 9) is now equal to the voltage V2 (<V1) dividedthrough the resistors R81 and R82. Therefore, after the output signalhas changed, even if the input signal IN fluctuates because of theeffects of noise, variations in supply voltage, etc., no unwantedchanges occur in the output signal OUT because the margin against noiseis large. This serves to prevent the malfunctioning of the circuitoperating by receiving the output signal OUT.

[0109] Each of the above embodiments has been described as being appliedto a delay circuit that uses the rising of an input signal, but it willbe appreciated that the invention may be applied to a delay circuit thatuses the rising of an input signal with the polarity inverted, or to adelay circuit that uses both the rising and falling of an input signal.When using the rising of an input signal, the charging circuit isconfigured as a discharging circuit (charge/discharge means). Further,it will be noted that the delay circuit of each of the above embodimentscan be used, for example, as the delay circuit 100 in the flash EEPROMshown in FIG. 5.

[0110] As described in detail above, according to the present invention,by quickly moving the signal not contributing to the delay action of thedelay circuit away from the input threshold value of the next-stagecircuit, the chance of being subjected to the effects of noise, etc. canbe reduced, and circuit reliability can thus be enhanced. Furthermore,when the invention is applied to a semiconductor memory device or thelike having an auto power-down function, design freedom can beincreased.

[0111] Many different embodiments of the present invention may beconstructed without departing from the spirit and scope of the presentinvention, and it should be understood that the present invention is notlimited to the specific embodiments described in this specification,except as defined in the appended claims.

What is claimed is:
 1. A delay circuit comprising: a charge/dischargecircuit for moderating a slope of change of an input signal; and a logiccircuit, receiving a charge/discharge signal output from saidcharge/discharge circuit, for changing an output signal of said logiccircuit when the charge/discharge signal exceeds a threshold value ofsaid logic circuit, wherein: a time constant in said charge/dischargecircuit is varied in accordance with the change in the output signal ofsaid logic circuit.
 2. A delay circuit as claimed in claim 1 , whereinsaid charge/discharge circuit comprises a switch element whose one endis connected to an input of said logic circuit, and a capacitor elementwhose one end is connected to the other end of said switch element,wherein a switching operation of said switch element is controlled bythe output signal of said logic circuit to vary the time constant ofsaid charge/discharge circuit due to said capacitor element.
 3. A delaycircuit as claimed in claim 2 , wherein said switch element iscontrolled in such a manner as to be switched OFF by the output signalof said logic circuit when the output signal of said logic circuitchanges in response to said charge/discharge signal exceeding thethreshold value of said logic circuit.
 4. A delay circuit as claimed inclaim 2 , wherein there are provided a plurality of said capacitorelements whose connection to the input of said logic circuit iscontrolled by said switch element, and said plurality of capacitorelements are arranged in parallel with each other.
 5. A delay circuit asclaimed in claim 4 , wherein at least one of said plurality of capacitorelements is connected at one end to the other end of said switch elementand at the other end to a prescribed power supply line.
 6. A delaycircuit as claimed in claim 4 , wherein at least one of said pluralityof capacitor elements is connected at one end to the other end of saidswitch element and at the other end to an output of a driver circuitsupplied with a prescribed control signal.
 7. A delay circuit as claimedin claim 1 , wherein said charge/discharge circuit is inserted in aninput of said logic circuit, and comprises a resistor element forsupplying said input signal via said resistor element, and a switchelement disposed in parallel with said resistor element, wherein aswitching operation of said switch element is controlled by the outputsignal of said logic circuit to vary the time constant of saidcharge/discharge circuit due to said resistor element.
 8. A delaycircuit as claimed in claim 7 , wherein said switch element iscontrolled in such a manner as to be switched ON by the output signal ofsaid logic circuit when the output signal of said logic circuit changesin response to said charge/discharge signal exceeding the thresholdvalue of said logic circuit.
 9. A delay circuit as claimed in claim 7 ,wherein there are provided a plurality of said switch elements and aplurality of said resistor elements whose short-circuiting with theinput of said logic circuit is controlled by said switch element, andsaid plurality of switch elements and said plurality of resistorelements are respectively arranged in series with each other.
 10. Adelay circuit as claimed in claim 9 , wherein said plurality of switchelements for controlling the short-circuiting of said plurality ofresistor elements are each controlled for switching, by the outputsignal of said logic circuit.
 11. A delay circuit as claimed in claim 1, wherein said charge/discharge circuit includes a current source, and acurrent flowing through said current source is controlled by the outputsignal of said logic circuit.
 12. A delay circuit as claimed in claim 11, wherein the current flowing through said current source is controlledso that the current increases when the output signal of said logiccircuit changes in response to said charge/discharge signal exceedingthe threshold value of said logic circuit.
 13. A delay circuit asclaimed in claim 1 , wherein said logic circuit comprises a comparator,a first input terminal of which is supplied with the charge/dischargesignal from said charge/discharge circuit, and a second input terminalof which is supplied with a reference voltage, wherein a control iscarried out to vary the reference voltage in accordance with the outputsignal of said logic circuit.
 14. A delay circuit as claimed in claim 1, wherein said logic circuit comprises a CMOS inverter.
 15. A delaycircuit as claimed in claim 1 , wherein said capacitor element isconstituted as a CMOS capacitor.
 16. A semiconductor memory devicehaving: a cell matrix having a plurality of memory cells; a data latchfor latching readout data output from said cell matrix; an addresstransfer detection circuit for detecting an address signal change; adelay circuit, outputting a latch control signal to said data latch inaccordance with an output signal of said address transfer detectioncircuit, for controlling said data latch to output the readout data insynchronism with the latch control signal, wherein said delay circuitcomprises: a charge/discharge circuit for moderating a slope of changeof an input signal; and a logic circuit, receiving a charge/dischargesignal output from said charge/discharge circuit, for changing an outputsignal of said logic circuit when the charge/discharge signal exceeds athreshold value of said logic circuit, wherein: a time constant in saidcharge/discharge circuit is varied in accordance with the change in theoutput signal of said logic circuit.
 17. A semiconductor memory deviceas claimed in claim 16 , wherein said charge/discharge circuit comprisesa switch element whose one end is connected to an input of said logiccircuit, and a capacitor element whose one end is connected to the otherend of said switch element, wherein a switching operation of said switchelement is controlled by the output signal of said logic circuit to varythe time constant of said charge/discharge circuit due to said capacitorelement.
 18. A semiconductor memory device as claimed in claim 17 ,wherein said switch element is controlled in such a manner as to beswitched OFF by the output signal of said logic circuit when the outputsignal of said logic circuit changes in response to saidcharge/discharge signal exceeding the threshold value of said logiccircuit.
 19. A semiconductor memory device as claimed in claim 17 ,wherein there are provided a plurality of said capacitor elements whoseconnection to the input of said logic circuit is controlled by saidswitch element, and said plurality of capacitor elements are arranged inparallel with each other.
 20. A semiconductor memory device as claimedin claim 19 , wherein at least one of said plurality of capacitorelements is connected at one end to the other end of said switch elementand at the other end to a prescribed power supply line.
 21. Asemiconductor memory device as claimed in claim 19 , wherein at leastone of said plurality of capacitor elements is connected at one end tothe other end of said switch element and at the other end to an outputof a driver circuit supplied with a prescribed control signal.
 22. Asemiconductor memory device as claimed in claim 16 , wherein saidcharge/discharge circuit is inserted in an input of said logic circuit,and comprises a resistor element for supplying said input signal viasaid resistor element, and a switch element disposed in parallel withsaid resistor element, wherein a switching operation of said switchelement is controlled by the output signal of said logic circuit to varythe time constant of said charge/discharge circuit due to said resistorelement.
 23. A semiconductor memory device as claimed in claim 22 ,wherein said switch element is controlled in such a manner as to beswitched ON by the output signal of said logic circuit when the outputsignal of said logic circuit changes in response to saidcharge/discharge signal exceeding the threshold value of said logiccircuit.
 24. A semiconductor memory device as claimed in claim 22 ,wherein there are provided a plurality of said switch elements and aplurality of said resistor elements whose short-circuiting with theinput of said logic circuit is controlled by said switch element, andsaid plurality of switch elements and said plurality of resistorelements are respectively arranged in series with each other.
 25. Asemiconductor memory device as claimed in claim 24 , wherein saidplurality of switch elements for controlling the short-circuiting ofsaid plurality of resistor elements are each controlled for switching,by the output signal of said logic circuit.
 26. A semiconductor memorydevice as claimed in claim 16 , wherein said charge/discharge circuitincludes a current source, and a current flowing through said currentsource is controlled by the output signal of said logic circuit.
 27. Asemiconductor memory device as claimed in claim 16 , wherein the currentflowing through said current source is controlled so that the currentincreases when the output signal of said logic circuit changes inresponse to said charge/discharge signal exceeding the threshold valueof said logic circuit.
 28. A semiconductor memory device as claimed inclaim 16 , wherein said logic circuit comprises a comparator, a firstinput terminal of which is supplied with the charge/discharge signalfrom said charge/discharge circuit, and a second input terminal of whichis supplied with a reference voltage, wherein a control is carried outto vary the reference voltage in accordance with the output signal ofsaid logic circuit.
 29. A semiconductor memory device as claimed inclaim 16 , wherein said logic circuit comprises a CMOS inverter.
 30. Asemiconductor memory device as claimed in claim 16 , wherein saidcapacitor element is constituted as a CMOS capacitor.
 31. Asemiconductor memory device as claimed in claim 16 , wherein saidsemiconductor memory device is a flash EEPROM.